MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 1275

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x0030–0x0031 Reserved Register Space
0x0032–0x0033 Port Integration Module (PIM) Map 4 of 6
0x0034–0x003F Clock and Reset Generator (CRG) Map
Freescale Semiconductor
Address
Address
0x003C
0x003D
0x0030
0x0031
0x0032
0x0033
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
0x003B
0x003E
0x003F
POSTDIV
ARMCOP
Reserved
Reserved
CRGFLG
COPCTL
FORBYP
CRGINT
CLKSEL
PLLCTL
RTICTL
PORTK
REFDV
CTCTL
DDRK
Name
Name
SYNR
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DDRK7
RTDEC
PLLSEL
WCOP
Bit 7
Bit 7
RTIE
RTIF
CME
Bit 7
PK7
0
0
0
0
0
0
VCOFRQ[1:0]
REFFRQ[1:0]
MC9S12XE-Family Reference Manual Rev. 1.23
DDRK6
RSBCK
PLLON
RTR6
PORF
PSTP
Bit 6
Bit 6
PK6
0
0
0
0
0
0
0
6
WRTMASK
SYNDIV5
REFDIV5
DDRK5
XCLKS
RTR5
Bit 5
Bit 5
LVRF
FM1
PK5
0
0
0
0
0
5
0
0
0
Reserved For Factory Test
Reserved For Factory Test
SYNDIV4
REFDIV4
DDRK4
LOCKIE
LOCKIF
RTR4
Bit 4
Bit 4
FM0
PK4
0
0
0
0
0
4
0
0
SYNDIV3
REFDIV3
FSTWKP
DDRK3
PLLWAI
RTR3
LOCK
Bit 3
Bit 3
PK3
0
0
0
0
3
0
0
Appendix E Detailed Register Address Map
POSTDIV[4:0]]
SYNDIV2
REFDIV2
DDRK2
RTR2
Bit 2
Bit 2
PK2
ILAF
PRE
CR2
0
0
0
0
0
0
0
2
SYNDIV1
REFDIV1
DDRK1
RTIWAI
SCMIE
SCMIF
RTR1
Bit 1
Bit 1
PK1
PCE
CR1
0
0
0
0
0
1
SYNDIV0
REFDIV0
COPWAI
DDRK0
SCME
RTR0
Bit 0
Bit 0
SCM
Bit 0
PK0
CR0
0
0
0
0
0
0
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