MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 147

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Field
PTH
PTH
PTH
PTH
PTH
PTH
7
6
5
4
3
2
Port H general purpose input/output data—Data Register
Port H pin 7 is associated with the TXD signal of the SCI5 module and the SS signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 6 is associated with the RXD signal of the SCI5 module and the SCK signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 5 is associated with the TXD signal of the SCI4 module and the MOSI signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 4 is associated with the RXD signal of the SCI4 module and the MISO signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 3 is associated with the TXD signal of the SCI7 module and the SS signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 2 is associated with the RXD signal of the SCI7 module and the SCK signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Table 2-49. PTH Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
147