MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 166

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.81
2.3.82
166
RDR0AD1
RDR1AD1
Address 0x027C
Address 0x027D
Write: Anytime.
Write: Anytime.
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
RDR0AD17
RDR1AD17
Port AD1 reduced drive—Select reduced drive for Port AD1 outputs
This register configures the drive strength of Port AD1 output pins 15 through 8 as either full or reduced independent
of the function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port AD1 reduced drive—Select reduced drive for Port AD1 outputs
This register configures the drive strength of Port AD1 output pins 7 through 0 as either full or reduced independent
of the function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port AD1 Reduced Drive Register 0 (RDR0AD1)
Port AD1 Reduced Drive Register 1 (RDR1AD1)
0
0
7
7
RDR0AD16
RDR1AD16
Figure 2-79. Port AD1 Reduced Drive Register 0 (RDR0AD1)
Figure 2-80. Port AD1 Reduced Drive Register 1 (RDR1AD1)
0
0
6
6
Table 2-77. RDR0AD1 Register Field Descriptions
Table 2-78. RDR1AD1 Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
RDR0AD15
RDR1AD15
0
0
5
5
RDR0AD14
RDR1AD14
0
0
4
4
Description
Description
RDR0AD13
RDR1AD13
3
0
3
0
RDR0AD12
RDR1AD12
0
0
2
2
RDR0AD11
RDR1AD11
Access: User read/write
Access: User read/write
Freescale Semiconductor
0
0
1
1
RDR0AD10
RDR1AD10
0
0
0
0
(1)
(1)

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