MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 197

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2
3.3.2.1
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
The MMCCTL0 register is used to control external bus functions, like:
Freescale Semiconductor
Address: 0x000A PRR
1. ROMON is bit[0] of the register MMCTL1 (see
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
1. Disabled: feature always inactive.
2. Enabled: activity is controlled by the appropriate register bit value.
W
R
Availability of chip selects. (See
Control of different external stretch mechanism. For more detail refer to the S12X_EBI
BlockGuide.
CS0E[1:0], CS1E[1:0],
CS2E[1:0], CS3E[1:0]
CS3E1
Register Descriptions
MMC Control Register (MMCCTL0)
Register Bit
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
= Unimplemented or Reserved
CS3E0
0
6
Figure 3-3. MMC Control Register (MMCCTL0)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 3-5. Chip Selects Function Activity
Disabled
CS2E1
NS
5
0
Table 3-5
Figure
(1)
Disabled
3-10)
CAUTION
CS2E0
SS
0
4
and
Table
Enabled
CS1E1
NX
3-6)
Chip Modes
0
3
(2)
Chapter 3 Memory Mapping Control (S12XMMCV4)
Disabled
ES
CS1E0
2
0
Enabled
EX
CS0E1
0
1
Disabled
ST
ROMON
CS0E0
0
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1