MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 242

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 4 Memory Protection Unit (S12XMPUV1)
4.4.1.1
If the memory ranges of two protection descriptors defined for the same bus-master overlap, the access
restrictions for the overlapped memory range are accumulated. For example:
4.4.1.2
As mentioned in the bit description of the Access Error Flag (AEF) in the MPUFLG register
there is an additional memory range implicitly defined only while the AEF bit is set: The CPU in
supervisor state can read from and write to the peripheral register space even if there is no memory
protection descriptor explicitly allowing this. This is to prevent the case that the CPU cannot clear the AEF
bit if the registers are write protected for the CPU in supervisor state.
The register address space containing the PAGE registers (EPAGE, RPAGE, GPAGE, PPAGE) at 0x0010−
0x0017 gets special treatment. It is defined like this:
4.4.1.3
Some bus-masters (CPU, XGATE) do a pre-fetch of program-code past the current instruction. The
S12XCPU pre-fetches two words past the current instruction, the XGATE pre-fetches one word, even if
the pre-fetched code is not executed. The MPU module has no way of knowing this at the time when the
pre-fetch cycles occur. Therefore this will result in an access violation if the op-code pre-fetch accesses a
memory range marked as “No-Execute” (NEX=1). This must be taken into account when defining memory
242
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
a memory protection descriptor defines memory range 0x40_0000−0x41_FFFF as WP=1, NEX=0
(read and execute)
another descriptor defines memory range 0x41_0000−0x43_FFFF as WP=0, NEX=1 (read and
write)
the resulting access rights for the overlapping range 0x41_0000−0x41_FFFF are WP=1, NEX=1
(read only)
The S12X CPU can always read and write these registers, regardless of the configuration in the
descriptors.
XGATE or Master3 (if available) are never allowed to read or write these registers, even if the
descriptor configuration allows accesses for other masters than the S12X CPU.
Overlapping Descriptors
Implicitly defined memory descriptors
Op-code pre-fetch cycles and the NEX bit
Configuring the lower boundary address of a descriptor to be higher than the
upper boundary address of a descriptor causes this descriptor to be ignored
by the comparator block. This effectively disables the descriptor.
Avoid changing descriptors while they are in active use to validate accesses
from bus-masters. This can be done by temporarily disabling the affected
master during the update (XGATE, Master 3, switch S12X CPU states).
Otherwise accesses from bus-masters affected by a descriptor which is
updated concurrently could yield undefined results.
MC9S12XE-Family Reference Manual , Rev. 1.23
NOTE
NOTE
Freescale Semiconductor
(Table
4-3),

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