MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 263

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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5.5.2.2
This mode is used for emulation systems in which the target application is operating in normal expanded
mode.
If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals
UDS, LDS, RE, and WE from the ADDR0, LSTRB, and RW signals.
Figure 5-6
The timings of accesses with 1 stretch cycle are shown in
The associated timing numbers are given in
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
ECLKX2 rising edges have the same timing as ECLK edges.
The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing
for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’
Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’
shows the PRU connection with the available external bus signals in an emulator application.
Example 2b: Emulation Expanded Mode
ADDR[22:20]/ACC[2:0]
ADDR[22:0]/IVD[15:0]
Figure 5-6. Application in Emulation Expanded Mode
S12X_EBI
MC9S12XE-Family Reference Manual Rev. 1.23
ADDR[19:16]/
IQSTAT[3:0]
DATA[15:0]
ECLKX2
CS[3:0]
LSTRB
EWAIT
ECLK
RW
EMULMEM
PRU
Emulator
PRR
UDS
LDS
WE
RE
Chapter 5 External Bus Interface (S12XEBIV4)
Ports
263

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