MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 272

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 6 Interrupt (S12XINTV2)
6.3.2.3
Read: Anytime
Write: Anytime
6.3.2.4
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the
block of eight interrupt requests (out of 128) selected by the interrupt configuration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
configuration data register of the vector with the highest address, respectively.
272
Address: 0x0127
INT_CFADDR[7:4]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
Field
R
7–4
Interrupt Request Configuration Address Register (INT_CFADDR)
Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
0
7
Priority
Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal
value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt
vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector
requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.
Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to
high
low
Figure 6-5. Interrupt Configuration Address Register (INT_CFADDR)
= Unimplemented or Reserved
INT_CFDATA0–7 will be ignored and read accesses will return all 0.
INT_CFADDR[7:4]
0
6
XILVL2
0
0
0
0
1
1
1
1
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 6-7. INT_CFADDR Field Descriptions
Table 6-6. XGATE Interrupt Priority Levels
XILVL1
5
0
0
0
1
1
0
0
1
1
XILVL0
1
4
0
1
0
1
0
1
0
1
Description
Interrupt request is disabled
0
0
3
Priority level 1
Priority level 2
Priority level 3
Priority level 4
Priority level 5
Priority level 6
Priority level 7
Meaning
2
0
0
Freescale Semiconductor
0
0
1
0
0
0

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