MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 285

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.1
Register Global Address 0x7FFF01
1. ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
2. CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when
3. UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
Freescale Semiconductor
Special Single-Chip Mode
0x7FFF0A
0x7FFF0B
0x7FFF07
0x7FFF08
0x7FFF09
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Address
fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
secured if emulation modes available.
else it is 0 and can only be read if not secure (see also bit description).
Global
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Emulation Modes
All Other Modes
(if modes available)
BDMCCRH R
BDMGPR
Reserved
Reserved
Reserved
Register
BDM Status Register (BDMSTS)
Name
Reset
W
R
W
W
W
W
W
R
R
R
R
ENBDM
0
BGAE
7
1
0
0
(1)
Bit 7
Figure 7-2. BDM Register Summary (continued)
X
0
0
0
0
Figure 7-3. BDM Status Register (BDMSTS)
MC9S12XE-Family Reference Manual Rev. 1.23
= Unimplemented, Reserved
= Always read zero
BDMACT
= Unimplemented, Reserved
= Indeterminate
BGP6
1
0
0
6
6
0
0
0
0
BGP5
0
0
0
0
5
5
0
0
0
0
SDV
BGP4
0
0
0
4
4
0
0
0
0
Chapter 7 Background Debug Module (S12XBDMV2)
TRACE
BGP3
3
0
0
0
3
0
0
0
0
0
= Implemented (do not alter)
= Implemented (do not alter)
= Always read zero
CLKSW
CCR10
BGP2
1
0
0
2
(2)
2
0
0
0
UNSEC
CCR9
BGP1
0
0
0
1
(3)
1
0
0
0
CCR8
BGP0
Bit 0
0
0
0
0
0
0
0
0
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