MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 313

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
DBGBRK
XGSBPE
COMRV
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
BDM
3–2
1–0
5
4
XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is
passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can
request an CPU12X breakpoint depending on the state of this bit.
0 XGATE S/W breakpoint request is disabled
1 XGATE S/W breakpoint request is enabled
Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled
by the ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint
to either CPU12X or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the
breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is
generated immediately. Please refer to
independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the CPU12X independent
of the DBGBRK bit field configuration. See
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
DBGBRK
COMRV
00
01
10
11
00
01
10
11
Table 8-5. DBGC1 Field Descriptions (continued)
No breakpoint generated
XGATE breakpoint generated
CPU12X breakpoint generated
Breakpoints generated for CPU12X and XGATE
MC9S12XE-Family Reference Manual Rev. 1.23
Visible Comparator
Comparator A
Comparator B
Comparator C
Comparator D
Table 8-6. DBGBRK Encoding
Table 8-7. COMRV Encoding
Section 8.4.7
Resource Halted by Breakpoint
Table
8-6.
Description
for further details. XGATE software breakpoints are
Visible Register at 0x0027
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
Chapter 8 S12X Debug (S12XDBGV3) Module
8-7.
313

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