MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 318

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.6
Read: Anytime
Write: Never
318
Address: 0x0026
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
CNT[6:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
POR
6–0
W
R
1. This applies to Normal/Loop1/PurePC Modes when tracing from either CPU12X or XGATE only.
TBF (DBGSR)
Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
Table 8-20
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-
trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The
DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus
should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of
valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when
reading from the trace buffer.
Debug Count Register (DBGCNT)
0
0
0
7
0
0
0
0
1
1
= Unimplemented or Reserved
shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
—
0
6
CNT[6:0]
0000000
0000001
0000010
0000100
0000110
1111100
1111110
0000000
0000010
1111110
Figure 8-8. Debug Count Register (DBGCNT)
..
..
..
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 8-19. DBGCNT Field Descriptions
Table 8-20. CNT Decoding Table
—
5
0
ARM bit will be cleared and the tracing session ends.
oldest data has been overwritten by most recent data
64 lines valid; if using Begin trigger alignment,
—
0
4
Description
32 bits of one line valid
CNT
—
64 lines valid,
No data valid
62 lines valid
63 lines valid
0
3
Description
2 lines valid
3 lines valid
1 line valid
..
—
2
0
(1)
Freescale Semiconductor
—
0
1
—
0
0