MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 382

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 10 XGATE (S12XGATEV3)
10.6.1.0.1
Debug mode can be entered in four ways:
382
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. Setting XGDBG to "1"
Single Stepping
Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core
registers will be updated accordingly.
Write accesses to the XGCHID register and the XGCHPL register
XGATE threads can be initiated and terminated through a 16 write access to the XGCHID and the
XGCHPL register or through a 8 bit write access to the XGCHID register. Detailed operation is
shown in
can be executed by leaving debug mode.
1. 8 bit write access to XGCHID
XGCHID
1..127
1..127
Register Content
0
0
Even though zero is not a valid interrupt priority level of the S12X_INT
module, a thread of priority level 0 can be initiated in debug mode. The
XGATE handles requests of priority level 0 in the same way as it handles
requests of priority levels 1 to 3.
All channels 1 to 127 can be initiated by writing to the XGCHID register,
even if they are not assigned to any peripheral module.
In Debug Mode the XGATE will ignore all requests from peripheral
modules.
Entering Debug Mode
Table
Table 10-22. Initiating and Terminating Threads in Debug Mode
XGCHPL
10-22. Once a thread has been initiated it’s code can be either single stepped or it
All other combinations
0..3
0..7
0
0
MC9S12XE-Family Reference Manual , Rev. 1.23
XGCHID
1..127
1..127
1..127
Single Cycle Write
0
Access to...
XGCHPL
NOTE
NOTE
NOTE
0..7
4..7
0..7
-
-
(1)
1
Resume interrupted thread or become idle if
no interrupted thread is pending
Terminate current thread.
Interrupt current thread
Set XGCHPL to 0x01
Initiate new thread
Initiate new thread
Initiate new thread
Set new XGCHPL
Set new XGCHPL
Set new XGCHID
Set new XGCHID
Set new XGCHID
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Action
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