MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 512

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
512
ETRIGCH[3:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SMP_DIS
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
3–0
4
1. Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
ETRIGSEL
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
ETRIGCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
Table 13-4. ATDCTL1 Field Descriptions (continued)
Table 13-6. External Trigger Channel Select Coding
SRES1
0
0
1
1
MC9S12XE-Family Reference Manual , Rev. 1.23
ETRIGCH2
Table 13-5. A/D Resolution Coding
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
SRES0
0
1
0
1
ETRIGCH1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
ETRIGCH0
A/D Resolution
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10-bit data
12-bit data
Reserved
8-bit data
Table
13-6.
External trigger source is
ETRIG0
Reserved
Reserved
ETRIG1
ETRIG2
ETRIG3
AN10
AN11
AN12
AN13
AN14
AN15
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
Freescale Semiconductor
(1)
1
1
1

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