MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 532

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.2.3
This pin serves as input capture or output compare for channel 5.
14.2.4
This pin serves as input capture or output compare for channel 4.
14.2.5
This pin serves as input capture or output compare for channel 3.
14.2.6
This pin serves as input capture or output compare for channel 2.
14.2.7
This pin serves as input capture or output compare for channel 1.
14.2.8
This pin serves as input capture or output compare for channel 0.
14.3
This section provides a detailed description of all memory and registers.
14.3.1
The memory map for the ECT module is given below in the
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
14.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
532
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Memory Map and Register Definition
IOC5 — Input Capture and Output Compare Channel 5
IOC4 — Input Capture and Output Compare Channel 4
IOC3 — Input Capture and Output Compare Channel 3
IOC2 — Input Capture and Output Compare Channel 2
IOC1 — Input Capture and Output Compare Channel 1
IOC0 — Input Capture and Output Compare Channel 0
Module Memory Map
Register Descriptions
For the description of interrupts see
MC9S12XE-Family Reference Manual Rev. 1.23
NOTE
Section 14.4.3, “Interrupts”.
Table
14-2. The address listed for each register
Freescale Semiconductor

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