MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 547

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA
bit in
Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers, instead of
generating an interrupt for every capture.
14.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
C[7:0]F
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7:0
Section 14.3.2.6, “Timer System Control Register 1
W
W
R
R
C7F
Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or
output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be
set by 8-bit pulse accumulators PAC3–PAC0.
If the delay counter is enabled, the CxF flag will not be set until after the delay.
TOF
0
0
7
7
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
= Unimplemented or Reserved
C6F
0
0
0
6
6
Figure 14-18. Main Timer Interrupt Flag 1 (TFLG1)
Figure 14-19. Main Timer Interrupt Flag 2 (TFLG2)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-17. TFLG1 Field Descriptions
C5F
5
0
5
0
0
(TSCR1)”.
C4F
NOTE
0
0
0
4
4
Description
(TSCR1)”).
C3F
0
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Section 14.3.2.6, “Timer
C2F
2
0
2
0
0
C1F
0
0
0
1
1
C0F
0
0
0
0
0
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