MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 557

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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All bits reset to zero.
14.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR)
Read: Anytime
Write: Anytime.
All bits reset to zero.
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN
is set, PA3EN and PA2EN have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN
is set, PA1EN and PA0EN have no effect.
Freescale Semiconductor
Module Base + 0x0028
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
POLF[3:0]
PA[3:0]EN
Reset
MCZF
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
3:0
3:0
7
W
R
Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000.
The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing
mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in
Section 14.3.2.6, “Timer System Control Register 1
First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The first input capture has been caused by a falling edge.
1 The first input capture has been caused by a rising edge.
8-Bit Pulse Accumulator ‘x’ Enable
0 8-Bit Pulse Accumulator is disabled.
1 8-Bit Pulse Accumulator is enabled.
0
0
7
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
Figure 14-44. Input Control Pulse Accumulators Register (ICPAR)
= Unimplemented or Reserved
0
0
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-25. MCFLG Field Descriptions
Table 14-26. ICPAR Field Descriptions
5
0
0
(TSCR1)”.
NOTE
0
0
4
Description
Description
(TSCR1)”).
PA3EN
0
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Section 14.3.2.6, “Timer
PA2EN
2
0
PA1EN
0
1
PA0EN
0
0
557

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