MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 584

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
15.3.1.2
Read and write anytime
584
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reserved
ADR[7:1]
IBC[7:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
7:1
7:0
0
W
R
Module Base + 0x0001
IBC7
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
IIC Frequency Divider Register (IBFD)
0
7
Table
15-4.
IBC6
Figure 15-4. IIC Bus Frequency Divider Register (IBFD)
= Unimplemented or Reserved
0
6
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 15-4. I-Bus Tap and Prescale Values
IBC2-0
Table 15-2. IBAD Field Descriptions
Table 15-3. IBFD Field Descriptions
(bin)
000
001
010
011
100
101
110
111
IBC5
5
0
IBC4
SCL Tap
(clocks)
0
4
10
12
15
5
6
7
8
9
Description
Description
IBC3
0
3
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
IBC2
2
0
Freescale Semiconductor
IBC1
0
1
IBC0
0
0