MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 77

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising
edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MMCCTL1
register on the rising edge of RESET.
1. Internal means resources inside the MCU are read/written.
1.4.1.1
Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus,
and port E provides bus control and status signals. This mode allows 16-bit external memory and
peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the
internal bus rate.
1.4.1.2
There is no external bus in this mode. The processor program is executed from internal memory. Ports A,
B,C,D, K, and most pins of port E are available as general-purpose I/O.
1.4.1.3
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin. There is
no external bus after reset in this mode.
1.4.1.4
Developers use this mode for emulation systems in which the users target application is normal expanded
mode. Code is executed from external memory or from internal memory depending on the state of
ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
Freescale Semiconductor
Normal single chip
Special single chip
Emulation single chip
Normal expanded
Emulation expanded
Special test
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM,
and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Chip Modes
Normal Expanded Mode
Normal Single-Chip Mode
Special Single-Chip Mode
Emulation of Expanded Mode
MODC
1
0
0
1
0
0
MC9S12XE-Family Reference Manual Rev. 1.23
Table 1-12. Chip Modes and Data Sources
MODB
0
0
0
0
1
1
MODA
0
0
1
1
1
0
ROMCTL
X
X
X
0
1
0
1
1
0
1
Chapter 1 Device Overview MC9S12XE-Family
EROMCTL
X
X
X
X
X
X
0
1
0
1
Internal
Emulation memory
Internal Flash
External application
Internal Flash
External application
Emulation memory
Internal Flash
External application
Internal Flash
Data Source
(1)
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