MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 854

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see
as indicated by reset condition ‘F’ in
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
854
FPHS[1:0]
FPLS[1:0]
FPOPEN
FPHDIS
FPLDIS
Offset Module Base + 0x0008
RNV[6]
Reset
Field
4–3
1–0
7
6
5
2
W
R
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x7F_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory beginning with global address
0x7F_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
in P-Flash memory as shown in
F
7
corresponding FPHS and FPLS bits
corresponding FPHS and FPLS bits
= Unimplemented or Reserved
RNV6
F
6
Figure 24-13. Flash Protection Register (FPROT)
MC9S12XE-Family Reference Manual , Rev. 1.23
Section 24.3.2.9.1, “P-Flash Protection Restrictions,” and Table
Table 24-19. FPROT Field Descriptions
FPHDIS
Figure
inTable
Table 24-20
F
5
Table
24-21. The FPHS bits can only be written to while the FPHDIS bit is set.
24-22. The FPLS bits can only be written to while the FPLDIS bit is set.
24-13. To change the P-Flash protection that will be loaded
for the P-Flash block.
F
4
FPHS[1:0]
Description
F
3
FPLDIS
F
2
Freescale Semiconductor
F
1
FPLS[1:0]
Table
24-23).
F
0
24-3)

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