MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 94

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 2 Port Integration Module (S12XEPIMV1)
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
2.1.2
The Port Integration Module includes these distinctive registers:
A standard port pin has the following minimum features:
Optional features supported on dedicated pins:
2.2
This section lists and describes the signals that do connect off-chip.
94
Open drain for wired-or connections
Interrupt inputs with glitch filtering
Reduced input threshold to support low voltage applications
Port F associated with IIC, SCI and chip select outputs
Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, AD1, R, L, and
F when used as general-purpose I/O
Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, J, R, L, and F on per-pin basis
Control registers to enable/disable pull-up devices on Ports AD0 and AD1 on per-pin basis
Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis
and on BKGD pin
Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, AD1, R, L,
and F on per-pin basis
Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on per-
port basis
Control registers to enable/disable open-drain (wired-or) mode on Ports S, M, and L
Interrupt flag register for pin interrupts on Ports P, H, and J
Control register to configure IRQ pin operation
Free-running clock outputs
Input/output selection
5V output drive with two selectable drive strengths
5V digital and analog input
Input with selectable pull-up or pull-down device
External Signal Description
Features
This document assumes the availability of all features (208-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary in the SOC Guide.
MC9S12XE-Family Reference Manual , Rev. 1.23
NOTE
Freescale Semiconductor

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