DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 153
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.4
5.4.1
There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to
leave software standby mode.
(1)
Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by
the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on
the NMI pin.
When an NMI interrupt is generated, the interrupt controller determines that an error has occurred,
and performs the following procedure.
• Sets the ERR bit of DTCCR in the DTC to 1.
• Sets the ERRF bit of DMDR_0 in the DMAC to 1
• Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate
(2)
An IRQn interrupt is requested by a signal input on pins IRQ11 to IRQ0. IRQn (n = 11 to 0) have
the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by
Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings,
and does not change regardless of the output setting. However, when a pin is used as an external
interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the
corresponding DDR bit to 0.
transfer
edge, rising edge, or both edges, on pins IRQn.
software. The bit manipulation instructions and memory operation instructions should be used
to clear the flag.
NMI Interrupts
IRQn Interrupts
Interrupt Sources
External Interrupts
Rev.1.00 Sep. 08, 2005 Page 103 of 966
Section 5 Interrupt Controller
REJ09B0219-0100
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