DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 572
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 12 8-Bit Timers (TMR)
12.5.4
TCNT is cleared when compare match A or B occurs, depending on the settings of the bits
CCLR1 and CCLR0 in TCR. Figure 12.11 shows the timing of this operation.
12.5.5
TCNT is cleared at the rising edge or high level of an external reset input, depending on the
settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figure
12.12 and Figure 12.13 shows the timing of this operation.
Note: * Clearing by an external reset is available only in units 0 and 1.
Rev.1.00 Sep. 08, 2005 Page 522 of 966
REJ09B0219-0100
Timing of Counter Clear by Compare Match
Timing of TCNT External Reset*
P
Compare match
signal
TCNT
Figure 12.12 Timing of Clearance by External Reset (Rising Edge)
Figure 12.13 Timing of Clearance by External Reset (High Level)
P
External reset
input pin
Clear signal
Clear signal
TCNT
P
External reset
input pin
TCNT
Figure 12.11 Timing of Counter Clear by Compare Match
N – 1
N – 1
N
N
N
H'00
H'00
H'00
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