DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 602
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 602 of 1020
- Download datasheet (6Mb)
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
14.3.3
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
already been written to TDR when one frame of data is transmitted, the SCI transfers the written
data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at
all times, to achieve reliable serial transmission, write transmit data to TDR for only once after
confirming that the TDRE bit in SSR is set to 1.
14.3.4
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
automatically transfers transmit data from TDR to TSR, and then sends the data to the TxD pin.
TSR cannot be directly accessed by the CPU.
14.3.5
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bits in SMR have different functions in normal mode and smart card interface mode.
• When SMIF in SCMR = 0
• When SMIF in SCMR = 1
Rev.1.00 Sep. 08, 2005 Page 552 of 966
REJ09B0219-0100
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Transmit Data Register (TDR)
Transmit Shift Register (TSR)
Serial Mode Register (SMR)
R/W
R/W
R/W
C/A
GM
7
1
7
0
7
0
CHR
R/W
R/W
R/W
BLK
6
0
6
1
6
0
R/W
R/W
R/W
PE
PE
5
1
5
0
5
0
R/W
R/W
R/W
O/E
O/E
4
1
4
0
4
0
STOP
BCP1
R/W
R/W
R/W
3
0
3
0
3
1
BCP0
R/W
R/W
R/W
MP
2
1
2
0
2
0
CKS1
CKS1
R/W
R/W
R/W
1
0
1
0
1
1
CKS0
CKS0
R/W
R/W
R/W
0
1
0
0
0
0
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