M30853FHFP#U3 Renesas Electronics America, M30853FHFP#U3 Datasheet - Page 541
M30853FHFP#U3
Manufacturer Part Number
M30853FHFP#U3
Description
IC M32C MCU FLASH 384K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30853FHFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FHFP#U3M30853FHFP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FHFP#U3M30853FHFP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
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Rev.
REVISION HISTORY
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401
Intelligent I/O
• Figure 22.1 Intelligent I/O Block Diagram BE1
• Figure 22.2 Intelligent I/O Communication Block Diagram Diagram modified
• Figure 22.13 Timer Measurement Function (1) The second condition modified
• Table 22.8 Waveform Generating Function Associated Register Settings
• Figure 22.20 G0RB and G1RB Registers Value after reset modified
• Figure 22.22 G0MR and G1MR Registers UFORM bit name changed
• Figure 22.23 G0EMR and G1EMR Registers Bit 0 modifed to RW
• Figure 22.24 G1ETC Register Bits 2 to 0 function changed
• Figure 22.27 G1IRF Register Note 2 modified
• Table 22.19 Pin Settings (4) P15
CAN Module
• Table 23.1 CAN Module Specifications Time Stamp Function specification
• Figure 23.2 Message Slot Buffer and Message Slot Diagram modified
• Table 23.2 Pin Settings P8
• Figure 23.3 C0CTLR0 and C1CTLR0 Registers Note 3 added
• 23.1.1.3 BASICCAN Bit Procedure (5) modified
• 23.1.1.6 ECRESET Bit The CAN0
• 23.1.6.5 SJW1 and SJW0 Bits Description modified
• Figure 23.9 C0BRP and C1BRP Registers Value after reset modified
• 23.1.16.1 CMOD Bit Note 1 modified
• Subsection description modified
• Subsection description modified
• Figure 23.39 Example of CAN Data Frame Receive Operation Diagram
• Figure 23.40 Operation Timing when CAN Bus Error Occurs Diagram modified
• 23.4.2.2 When the INTSEL Bit is Set to "1" Description modified
Programmable I/O Ports
• 24.3 Function Select Register Aj (PSJ Register) (i=0 to 5, 8, 9) changed to (i=0
• Figure 24.2 Programmable I/O Ports (2) Diagram modified
• Figure 24.6 P0 to P15 Registers Note 4 modified
• Figure 24.15 PUR2 Register Note 3 deleted
• Figure 24.17 IPS Register Note 2 modified
Flash Memory Version
• Figure 25.4 FMR0 Register Note 5 modified
• 25.3.3.4 FMSTP Bit Description modified
Note modified
modified
modified
to 3, 5, 8, 9)
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
C-22
Description
3
setting with the IPS register changed
OUT
Summary
2
setting with the PS9 register changed
pin on Note 2 modified to the CANi
OUT
added
OUT
pin
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