MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 137

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Technical Data — MC68HC912DT128A
10.1 Contents
10.2 Introduction
MC68HC912DT128A — Rev 4.0
MOTOROLA
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
CPU12 exceptions include resets and interrupts. Each exception has an
associated 16-bit vector, which points to the memory location where the
routine that handles the exception is located. Vectors are stored in the
upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
Freescale Semiconductor, Inc.
For More Information On This Product,
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .141
Interrupt test registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Go to: www.freescale.com
Resets and Interrupts
Section 10. Resets and Interrupts
Technical Data
137

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