MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 179

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLKSEL — Clock Generator Clock select Register
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
Bit 7
0
0
BCSP
6
0
Read and write anytime. Exceptions are listed below for each bit.
BCSP — Bus Clock Select PLL
BCSS — Bus Clock Select Slow
MCS — Module Clock Select
BCSP and BCSS bits determine the clock used by the main system
including the CPU and buses.
Cannot be set when PLLON = 0. In limp-home mode, the output of
BCSP is forced to 1, but the BCSP bit reads the latched value.
This bit has no effect when BCSP is set.
This bit determines the clock used by the ECT module and the baud
rate generators of the SCIs. In limp-home mode, the output of MCS is
forced to 0, but the MCS bit reads the latched value.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = SYSCLK is derived from the crystal clock or from SLWCLK.
1 = SYSCLK source is the PLL.
0 = SYSCLK is derived from the crystal clock EXTALi.
1 = SYSCLK source is the Slow clock SLWCLK.
0 = M clock is the same as PCLK.
1 = M clock is derived from Slow clock SLWCLK.
BCSS
5
0
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Clock Functions
4
0
0
3
0
0
Limp-Home and Fast STOP Recovery modes
MCS
2
0
1
0
0
Bit 0
0
0
Clock Functions
Technical Data
$003D
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