MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 22

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

List of Tables
Technical Data
22
14-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . . 230
14-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 240
14-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 240
15-1 Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 255
15-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .256
15-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
16-1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
16-2 Loop Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
16-3 SS Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
16-4 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
17-1 IIC Tap and Prescale Values . . . . . . . . . . . . . . . . . . . . . . . . .310
17-2 IIC Divider and SDA Hold values . . . . . . . . . . . . . . . . . . . . . . 311
18-1 msCAN12 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .337
18-2 msCAN12 vs. CPU operating modes . . . . . . . . . . . . . . . . . . . 338
18-3 Data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
18-4 Synchronization jump width . . . . . . . . . . . . . . . . . . . . . . . . . .354
18-5 Baud rate prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
18-6 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18-7 Time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18-8 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .362
18-9 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . . 362
19-1 Result Data Formats Available . . . . . . . . . . . . . . . . . . . . . . . . 379
19-2 Left Justified ATD Output Codes . . . . . . . . . . . . . . . . . . . . . . 380
19-3 ATD Response to Background Debug Enable . . . . . . . . . . . . 382
19-4 Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .383
19-5 Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
19-6 Conversion Sequence Length Coding . . . . . . . . . . . . . . . . . .385
19-7 Result Register Assignment for Different Conversion
19-8 Special Channel Conversion Select Coding . . . . . . . . . . . . . .386
19-9 Analog Input Channel Select Coding . . . . . . . . . . . . . . . . . . .387
19-10 Multichannel Mode Result Register Assignment (MULT=1) . .388
20-1 IPIPE Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
20-2 Hardware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
20-3 BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . .403
20-4 BDM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
20-5 TTAGO Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
20-6 REGN Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
Freescale Semiconductor, Inc.
For More Information On This Product,
Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
Go to: www.freescale.com
List of Tables
MC68HC912DT128A — Rev 4.0
MOTOROLA