MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 235

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912DT128A — Rev 4.0
MOTOROLA
PWPERx — PWM Channel Period Registers
PWPER0
PWPER1
PWPER2
PWPER3
RESET:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
The PWM counters are not reset when PWM channels are disabled. The
counters must be reset prior to a new enable.
Each counter may be read any time without affecting the count or the
operation of the corresponding PWM channel. Writes to a counter cause
the counter to be reset to $00 and force an immediate load of both duty
and period registers with new values. To avoid a truncated PWM period,
write to a counter while the counter is disabled. In left-aligned output
mode, resetting the counter and starting the waveform output is
controlled by a match between the period register and the value in the
counter. In center-aligned output mode the counters operate as up/down
counters, where a match in period changes the counter direction. The
duty register changes the state of the output during the period to
determine the duty.
When a channel is enabled, the associated PWM counter starts at the
count in the PWCNTx register using the clock selected for that channel.
In special mode, when DISCP = 1 and configured for left-aligned output,
a match of period does not reset the associated PWM counter.
Read and write anytime.
The value in the period register determines the period of the associated
PWM channel. If written while the channel is enabled, the new value will
not take effect until the existing period terminates, forcing the counter to
reset. The new period is then latched and is used until a new period
value is written. Reading this register returns the most recent value
written. To start a new period immediately, write the new period value
6
6
6
6
6
1
Freescale Semiconductor, Inc.
For More Information On This Product,
5
5
5
5
5
1
Go to: www.freescale.com
Pulse Width Modulator
4
4
4
4
4
1
3
3
3
3
3
1
2
2
2
2
2
1
1
1
1
1
1
1
PWM Register Descriptions
Pulse Width Modulator
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
1
Technical Data
$004C
$004D
$004E
$004F
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