MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 265

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912DT128A — Rev 4.0
MOTOROLA
ICLAT — Input Capture Force Latch Action
FLMC — Force Load Register into the Modulus Counter Count Register
MCEN — Modulus Down-Counter Enable
MCPR1, MCPR0 — Modulus Counter Prescaler select
When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS ($AB) are set), a write one to this bit immediately forces the
contents of the input capture registers TC0 to TC3 and their
corresponding 8-bit pulse accumulators to be latched into the
associated holding registers. The pulse accumulators will be
automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will return always
zero.
This bit is active only when the modulus down-counter is enabled
(MCEN=1).
A write one into this bit loads the load register into the modulus
counter count register. This also resets the modulus counter
prescaler. Write zero to this bit has no effect.
When MODMC=0, counter starts counting and stops at $0000.
Read of this bit will return always zero.
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
Go to: www.freescale.com
Enhanced Capture Timer
MCPR1
0
0
1
1
MCPR0
0
1
0
1
Prescaler division rate
16
1
4
8
Timer Register Descriptions
Enhanced Capture Timer
Technical Data
265