MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 272

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PBFLG — Pulse Accumulator B Flag Register
PBCTL — 16-Bit Pulse Accumulator B Control Register
Enhanced Capture Timer
Technical Data
272
RESET:
RESET:
BIT 7
BIT 7
0
0
0
0
PBEN
6
0
0
6
0
Read or write any time.
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input pin
with IC0.
PBEN — Pulse Accumulator B System Enable
PBOVI — Pulse Accumulator B Overflow Interrupt enable
Read or write any time.
PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
1 = Pulse Accumulator B system enabled. The two 8-bit pulse
0 = interrupt inhibited
1 = interrupt requested if PBOVF is set
5
0
0
5
0
0
PAC0 can be enabled when their related enable bits in
ICPACR ($A8) are set.
accumulators PAC1 and PAC0 are cascaded to form the
PACB 16-bit pulse accumulator. When PACB in enabled, the
PACN1 and PACN0 registers contents are respectively the
high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPACR ($A8) have no
effect.
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Enhanced Capture Timer
4
0
0
4
0
0
3
0
0
3
0
0
2
0
0
2
0
0
MC68HC912DT128A — Rev 4.0
PBOVF
PBOVI
1
0
1
0
BIT 0
BIT 0
0
0
0
0
MOTOROLA
$00B1
$00B0