MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 280

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Multiple Serial Interface
16.4.1 Data Format
16.4.2 SCI Baud Rate Generation
Technical Data
280
The serial data format requires the following conditions:
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the M Clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
An idle-line in the high state before transmission or reception of a
message.
A start bit (logic zero), transmitted or received, that indicates the
start of each character.
Data that is transmitted or received least significant bit (LSB) first.
A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
This SCI supports hardware parity for transmit and receive.
Go to: www.freescale.com
SCI Baud Rate
Multiple Serial Interface
Desired
14400
19200
38400
Table 16-1. Baud Rate Generation
1200
2400
4800
9600
110
300
600
BR Divisor for
M = 4.0 MHz
2273
833
417
208
104
52
26
17
13
MC68HC912DT128A — Rev 4.0
BR Divisor for
M = 8.0 MHz
4545
2273
833
417
208
104
52
35
26
13
MOTOROLA

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