MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 305

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5.1 START Signal
17.5.2 Slave Address Transmission
17.5.3 Data Transfer
MC68HC912DT128A — Rev 4.0
MOTOROLA
NOTE:
When the bus is free, i.e. no master device is engaging the bus (both
SCL and SDA lines are at logical high), a master may initiate
communication by sending a START signal. As shown in
START signal is defined as a high-to-low transition of SDA while SCL is
high. This signal denotes the beginning of a new data transfer (each data
transfer may contain several bytes of data) and wakes up all slaves.
The first byte of data transfer immediately after the START signal is the
slave address transmitted by the master. This is a seven-bit calling
address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a calling address that matches the one transmitted
by the master will respond by sending back an acknowledge bit. This is
done by pulling the SDA low at the 9th clock (see
Once successful slave addressing is achieved, the data transfer can
proceed byte-by-byte in a direction specified by the R/W bit sent by the
calling master.
All transfers that come after an address cycle are referred to as data
transfers, even if they carry sub-address information for the slave
device.
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1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Slave address - No two slaves in the system may have the same
address. If the IIC is master, it must not transmit an address that
is equal to its own slave address. The IIC cannot be master and
slave at the same time. If however arbitration is lost during an
address cycle the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
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Inter IC Bus
Figure
Figure
17-2).
Technical Data
Inter IC Bus
IIC Protocol
17-2, a
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