MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 310

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Manufacturer
Quantity
Price
Part Number:
MC912DG128AMPVE
Manufacturer:
FREESCALE
Quantity:
2 902
Part Number:
MC912DG128AMPVE
Manufacturer:
FREESCALE
Quantity:
800
Part Number:
MC912DG128AMPVE
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC912DG128AMPVE
Manufacturer:
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Quantity:
800
Inter IC Bus
Technical Data
310
The number of clocks from the falling edge of SCL to the first tap
(Tap[1]) is defined by the values shown in the scl2tap column of
17-1, all subsequent tap points are separated by 2
the tap2tap column in
the SCL period and the SDA Tap is used to determine the delay from
the falling edge of SCL to SDA changing, the SDA hold time.
The serial bit clock frequency is equal to the CPU clock frequency
divided by the divider shown in
generate the divider values from the IBFD bits is:
The SDA hold delay is equal to the CPU clock period multiplied by the
SDA Hold value shown in
the SDA Hold value from the IBFD bits is:
Freescale Semiconductor, Inc.
IBC2-0
(bin)
000
001
010
011
100
101
110
111
For More Information On This Product,
SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )
SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3
Go to: www.freescale.com
SCL Tap
(clocks)
Table 17-1. IIC Tap and Prescale Values
10
12
15
5
6
7
8
9
Inter IC Bus
SDA Tap
(clocks)
Table
1
1
2
2
3
3
4
4
Figure
17-1. The SCL Tap is used to generated
Table
17-2. The equation used to generate
17-2. The equation used to
IBC5-3
(bin)
000
001
010
011
100
101
110
111
MC68HC912DT128A — Rev 4.0
(clocks)
scl2tap
IBC5-3
126
14
30
62
4
4
6
6
as shown in
MOTOROLA
(clocks)
tap2tap
128
16
32
64
1
2
4
8
Table

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