MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 316

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IBDR — IIC Bus Data I/O Register
Inter IC Bus
Technical Data
316
RESET:
Bit 7
NOTE:
D7
0
D6
6
0
IBIF — IIC Bus Interrupt Flag
RXAK — Received Acknowledge
.
Read and write anytime
In master transmit mode, when data is written to the IBDR a data transfer
is initiated. The most significant bit is sent first. In master receive mode,
reading this register initiates next byte data receiving. In slave mode, the
same functions are available after an address match has occurred.
In master transmit mode, the first byte of data written to IBDR following
assertion of MS/SL is used for the address transfer and should comprise
of the calling address (in position D7-D1) concatenated with the required
R/W bit (in position D0).
1. Complete one byte transfer (set at the falling edge of the 9th
2. Receive a calling address that matches its own specific address in
3. Arbitration lost.
The IBIF bit is set when an interrupt is pending, which will cause a
processor interrupt request provided IBIE is set. IBIF is set when one
of the following events occurs:
This bit must be cleared by software, writing a one to it, in the interrupt
routine.
The value of SDA during the acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates an acknowledge
signal has been received after the completion of 8 bits data
transmission on the bus. If RXAK is high, it means no acknowledge
signal is detected at the 9th clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Acknowledge received
1 = No acknowledge received
clock).
slave receive mode.
D5
5
0
Go to: www.freescale.com
D4
4
0
Inter IC Bus
D3
3
0
D2
2
0
MC68HC912DT128A — Rev 4.0
D1
1
0
Bit 0
D0
0
MOTOROLA
High
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