MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 332

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSCAN Controller
18.5 Identifier Acceptance Filter
Technical Data
332
a transmit interrupt. The transmit interrupt handler software can tell from
the setting of the ABTAK flag whether the message was actually aborted
(ABTAK=1) or sent in the meantime (ABTAK=0).
A very flexible programmable generic identifier acceptance filter has
been introduced in order to reduce the CPU interrupt loading. The filter
is programmable to operate in four different modes:
•
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Two identifier acceptance filters, each to be applied to the full 29
bits of the identifier and to the following bits of the CAN frame:
RTR, IDE, SRR. This mode implements a two filters for a full
length CAN 2.0B compliant extended identifier.
how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3) produces a
filter 0 hit. Similarly, the second filter bank (CIDAR4–7,
CIDMR4–7) produces a filter 1 hit.
Four identifier acceptance filters, each to be applied to a) the 11
bits of the identifier and the RTR bit of CAN 2.0A messages or b)
the 14 most significant bits of the identifier of CAN 2.0B messages.
Figure 18-4
CIDMR0–3) produces filter 0 and 1 hits. Similarly, the second filter
bank (CIDAR4–7, CIDMR4–7) produces filter 2 and 3 hits.
Eight identifier acceptance filters, each to be applied to the first 8
bits of the identifier. This mode implements eight independent
filters for the first 8 bit of a CAN 2.0A compliant standard identifier
or of a CAN 2.0B compliant extended identifier.
how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3) produces
filter 0 to 3 hits. Similarly, the second filter bank (CIDAR4–7,
CIDMR4–7) produces filter 4 to 7 hits.
Closed filter. No CAN message will be copied into the foreground
buffer RxFG, and the RXF flag will never be set.
Go to: www.freescale.com
MSCAN Controller
shows how the first 32-bit filter bank (CIDAR0–3,
MC68HC912DT128A — Rev 4.0
Figure 18-3
Figure 18-5
MOTOROLA
shows
shows