MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 353

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.13.3 msCAN12 Module Control Register (CMCR1)
MC68HC912DT128A — Rev 4.0
MOTOROLA
CMCR1
$0101
RESET
W
R
NOTE:
Bit 7
0
0
LOOPB — Loop Back Self Test Mode
WUPM — Wake-Up Mode
CLKSRC — msCAN12 Clock Source
The CMCR1 register can only be written if the SFTRES bit in CMCR0 is
set.
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver. The RxCAN input pin is ignored
and the TxCAN output goes to the recessive state (1). Note that in this
state the msCAN12 ignores the bit sent during the ACK slot of the
CAN frame Acknowledge field to insure proper reception of its own
message and will treat messages being received while in
transmission as received messages from remote nodes.
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see
Wake-Up
This flag defines which clock source the msCAN12 module is driven
from (only for system with CGM module; see
18-7).
Freescale Semiconductor, Inc.
6
0
0
For More Information On This Product,
0 = Normal operation
1 = Activate loop back self test mode
0 = msCAN12 will wake up the CPU after any recessive to
1 = msCAN12 will wake up the CPU only in case of dominant pulse
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
dominant edge on the CAN bus.
on the bus which has a length of at least approximately T
ECLK.
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Function).
5
0
0
MSCAN Controller
4
0
0
3
0
0
Programmer’s Model of Control Registers
LOOPB
2
0
Clock
WUPM
System,
Programmable
1
0
MSCAN Controller
Technical Data
CLKSRC
Figure
Bit 0
0
wup
353
.