MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 370

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog-to-Digital Converter
19.4 Functional Description
19.4.1 Analog Input Multiplexer
19.4.2 Sample Buffer Amplifier
Technical Data
370
NOTE:
The MCU can discover when result data is available in the result
registers with an interrupt on sequence complete or by polling the
conversion complete flags
ATD conversion modes should not be confused with MCU operating
modes such as STOP, WAIT, IDLE, RUN, DEBUG, and SPECIAL (test)
modes or with module defined operating modes such as power down,
fast flag clear, 8-bit resolution, 10-bit resolution, interrupt enable, clock
prescaler setting, and freeze modes; and finally do not confuse with
module result data formats such as right justify mode and left justify
mode.
The analog input multiplexer selects one of the 8 external analog input
channels to generate an analog sample. The input analog signals are
unipolar and must fall within the potential range of VSSA to VDDA
(analog electronics supply potentials).
A sample amplifier is used to buffer the input analog signal so that a
storage node can be quickly charged to the sample potential.
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WAIT is executed (if the ASWAI bit is activated)
STOP is executed.
The SCF bit is set after the completion of each sequence.
The CCF bit associated with each result register is set when that
register is loaded with result data.
Analog-to-Digital Converter
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MC68HC912DT128A — Rev 4.0
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