MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 403

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912DT128A — Rev 4.0
MOTOROLA
WRITE_NEXT
READ_NEXT
WRITE_PC
WRITE_SP
Command
READ_PC
READ_SP
WRITE_D
WRITE_X
WRITE_Y
READ_D
READ_X
READ_Y
TRACE1
TAGGO
GO
Opcode (Hex)
and executes them as they are received. The firmware commands are
shown in
Each of the hardware and firmware BDM commands start with an 8-bit
command code (opcode). Depending upon the commands, a 16-bit
address and/or a 16-bit data word is required as indicated in the tables
by the command. All the read commands output 16-bits of data despite
the byte/word implication in the command name.
The external host should wait 150 BDMCLK cycles for a non-intrusive
BDM command to execute before another command is sent. This delay
includes 128 BDMCLK cycles for the maximum delay for a free cycle.For
data read commands, the host must insert this delay between sending
the address and attempting to read the data.In the case of a write
command, the host must delay after the data portion, before sending a
new command, to be sure the write has finished.
The external host should delay about 32 target BDMCLK cycles between
a firmware read command and the data portion of these commands. This
allows the BDM firmware to execute the instructions needed to get the
requested data into the BDM SHIFTER register.
The external host should delay about 32 target BDMCLK cycles after the
data portion of firmware write commands to allow BDM firmware to
62
63
64
65
66
42
43
44
45
46
47
08
10
18
67
Freescale Semiconductor, Inc.
Table 20-3. BDM Firmware Commands
For More Information On This Product,
Table
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
Go to: www.freescale.com
Development Support
20-3.
None
None
None
Data
X = X + 2; Read next word pointed to by X
Read program counter
Read D accumulator
Read X index register
Read Y index register
Read stack pointer
X = X + 2; Write next word pointed to by X
Write program counter
Write D accumulator
Write X index register
Write Y index register
Write stack pointer
Go to user program
Execute one user instruction then return to BDM
Enable tagging and go to user program
Description
Background Debug Mode
Development Support
Technical Data
403