MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 405

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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20.4.4.2 Disabling the BDM lockout
20.4.5 BDM Registers
MC68HC912DT128A — Rev 4.0
MOTOROLA
NOTE:
Disabling the BDM lockout is only possible in special modes
(SMODN=0) except in special single chip. Follow the same steps as for
enabling the BDM lockout, but erase the SHADOW word.
At the next reset, the high byte of SHADOW word is loaded into the
EEMCR register. NOBDML bit in EEMCR will be set and BDM becomes
operational.
When the BDM lockout is enabled it is not possible to run code from the
reset vector in special single chip mode.
Seven BDM registers are mapped into the standard 64-Kbyte address
space when BDM is active. Mapping is shown in
The content of the INSTRUCTION register is determined by the type of
background command being executed.The STATUS register indicates
BDM operating conditions.The SHIFT register contains data being
received or transmitted via the serial interface. The ADDRESS register
4. Protect the SHADOW word by setting SHPROT bit in EEPROT
Freescale Semiconductor, Inc.
For More Information On This Product,
SHADOW word (location $0FC0); otherwise some regular
EEPROM array locations will not be visible. At the next reset, the
high byte of the SHADOW word is loaded into the EEMCR
register. NOBDML bit in EEMCR will be cleared and BDM will not
be operational.
register.
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$FF02 – $FF03
$FF04 – $FF05
Development Support
Address
$FF00
$FF01
$FF06
Table 20-4. BDM registers
BDM CCR Holding Register
BDM Instruction Register
BDM Address Register
BDM Status Register
BDM Shift Register
Register
Table
Background Debug Mode
Development Support
20-4.
Technical Data
405

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