MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 408

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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INSTRUCTION— BDM Instruction Register (hardware command explanation)
Development Support
20.4.5.2 INSTRUCTION - Hardware Instruction Decode
Technical Data
408
RESET:
BIT 7
H/F
0
DATA
6
0
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
. The hardware clears the INSTRUCTION register if 512 BDMCLK
cycles occur between falling edges from the host.
The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
H/F — Hardware/Firmware Flag
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM
communications.
If ECLK rate is slower than BDMCLK rate, CLKSW is ignored and
BDM system is forced to operate with ECLK.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = BDM system operates with ECLK.
0 = Firmware command
1 = Hardware command
R/W
5
0
Go to: www.freescale.com
Development Support
BKGND
4
0
W/B
3
0
BD/U
2
0
MC68HC912DT128A — Rev 4.0
1
0
0
BIT 0
0
0
MOTOROLA
$FF00

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