MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 445

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.2.7.3 Additional Features
22.2.7.4 S8CM bit
22.2.7.5 Writing to ATDxCTL4
MC68HC912DT128A — Rev 4.0
MOTOROLA
ATD flexibility has been increased with additional signed result, data
justification, single conversion selection and results location FIFO
features.
DJM & DSGN bits have been added to ATDxCTL2 register. Default
values are compatible with MC68HC912DG128 functionality.
FIFO & S1C bits have been added to ATDxCTL3 register. Default values
are compatible with MC68HC912DG128 functionality.
Bit S8CM in ATDxCTL5 is renamed S8C. Functionality is compatible
with S8CM but can now be modified by the new S1C bit in ATDxCTL3.
The default is compatible with MC68HC912DG128 functionality.
Writing to ATDxCTL4 aborts any ongoing conversion sequence and
initiates a new conversion sequence. Previously it only aborted ongoing
sequences leaving the ATD in idle mode (no conversion sequences
being processed). Writing to ATDxCTL2 or ADTxCTL3 also does not
abort an ongoing conversion sequence. Previously writing these
registers also aborted any ongoing sequence leaving the ATD in idle
mode .
This is unlikely to be a compatibility issue as applications mostly write
these registers to configure the ATD, closely followed by a write to
ATDxCTL5 to initiate a new conversion sequence which does abort any
ongoing conversion sequence and resets the appropriate flags.
To ensure compatibility, the application should not rely on ongoing
conversions being aborted. Also any interrupts from the completion of an
ongoing sequence should be masked and/or handled correctly.
Freescale Semiconductor, Inc.
Appendix: Changes from MC68HC912DG128
For More Information On This Product,
Go to: www.freescale.com
Significant changes from the MC68HC912DG128 (non-suffix device)
Appendix: Changes from MC68HC912DG128
Technical Data
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