MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 473

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Technical Data — MC68HC912DT128A
24.9 Changes in Rev. 4.0
24.10 Changes from Rev 2.0 to Rev 3.0
MC68HC912DT128A — Rev 4.0
MOTOROLA
Pinout and Signal
Flash Memory
Specifications
Descriptions
Registers
Electrical
Section
Section
Page (in Rev 3.0)
Page (in Rev 3.0)
This section lists the revision history of the document since the first
release. Data for previous internal drafts is unavailable.
Freescale Semiconductor, Inc.
42,
55,
437
116
117
120
122
46
48
54
68
For More Information On This Product,
43
60
Go to: www.freescale.com
Clock (SCK) High or Low Time, Master, t
t
Note about TEST pin updated
PLL loop filter connections diagram
Note added about consideration of crystal selection due to EMC
emissions
Description of TEST pin added as new section and to
Text added in
connection of RxCAN pins when MSCAN modules are not used.
FPOPEN bit added to EEMCR register
New paragraph added to overview about flash protection via
FPOPEN bit
Last part of FEEMCR opening paragraph changed to ‘if HVEN or
PGM or ERAS in the FEECTL register is set’
Changes made to the Flash programming description for
clarification of aligned words
New section
cyc
Revision History
− 60 to t
cyc
7.11 Flash protection bit FPOPEN
Table 3-2
− 30.
Description of change
Description of change
and Port CAN pin descriptions about non-
Revision History
(Figure
wsck
3-4) updated
changed from
added
Technical Data
Table 3-2
473

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