MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 63

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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3.5.14 Port S
3.5.15 Port T
MC68HC912DT128A — Rev 4.0
MOTOROLA
Setting the RDPP bit in the PWCTL register configures all port P outputs
to have reduced drive levels. Levels are at normal drive capability after
reset. The PWCTL register can be read or written anytime after reset.
Refer to
Port S is the 8-bit interface to the standard serial interface consisting of
the two serial communications interfaces (SCI1 and SCI0) and the serial
peripheral interface (SPI) subsystems. Port S pins are available for
general-purpose I/O when standard serial functions are not enabled.
Port S pins serve several functions depending on the various internal
control registers. If WOMS bit in the SC0CR1register is set, the P-
channel drivers of the output buffers are disabled (wire-or mode) for pins
0 through 3. If SWOM bit in the SP0CR1 register is set, the P-channel
drivers of the output buffers are disabled (wire-or mode) for pins 4
through 7. The open drain control affects both the serial and the general-
purpose outputs. If the RDPS bit in the SP0CR2 register is set, Port S
pin drive capabilities are reduced. If PUPS bit in the SP0CR2 register is
set, a pull-up device is activated for each port S pin programmed as a
general purpose input. If the pin is programmed as a general-purpose
output, the pull-up is disconnected from the pin regardless of the state of
PUPS bit. See
This port provides eight general-purpose I/O pins when not enabled for
input capture and output compare in the timer and pulse accumulator
subsystem. The TEN bit in the TSCR register enables the timer function.
The pulse accumulator subsystem is enabled with the PAEN bit in the
PACTL register.
Register DDRT determines pin direction of port T when used for general-
purpose I/O. When DDRT bits are set, the corresponding pin is
configured for output. On reset the DDRT bits are cleared and the
corresponding pin is configured for input.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pulse Width
Pinout and Signal Descriptions
Go to: www.freescale.com
Multiple Serial
Modulator.
Interface.
Pinout and Signal Descriptions
Technical Data
Port Signals
63

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