M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 151
M30833FJGP#U3
Manufacturer Part Number
M30833FJGP#U3
Description
IC M32C/83 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
R8C
Maximum Speed
32 MHz
Operating Supply Voltage
5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
3
. v
J
Figure 13.1 RLVL Register
2
0
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
Exit Priority Register
b7
NOTES:
3 .
1
u
, 1
3
p
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not
4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register
b6
1
2
(
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0".
change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the
DMAII bit to "1".
after setting the DMA II bit to "0".
M
0
b5
0
3
6
2
b4
C
8 /
Page 126
b3
, 3
b2
M
b1
3
2
C
b0
f o
8 /
4
(b7 - b6)
3
Symbol
8
RLVL0
RLVL1
RLVL2
DMA II
) T
FSIT
8
(b4)
Bit
Symbol
RLVL
Stop/Wait Mode Exit
Minimum Interrupt Priority
Level Control Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMAC II Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
High-Speed Interrupt
Set Bit
(2)
Bit Name
Address
009F
16
(1)
(4)
b2 b1 b0
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt priority level 7 is used
1: Interrupt priority level 7 is used
0: Interrupt priority level 7 is used
1: Interrupt priority level 7 is used
for normal interrupt
for high-speed interrupt
for interrupt
for DMAC II transfer
After Reset
XXXX 0000
Function
2
(3)
RW
RW
RW
RW
RW
RW
13. DMACII
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