MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 128

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.4.3 Load/Store Unit (LSU)
3.4.4 Floating-Point Unit (FPU)
MPC555
USER’S MANUAL
The IU also includes the integer exception register (XER) and the general-purpose
register file.
IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–
BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require
multiple clock cycles to execute. IMUL–IDIV is pipelined for multiply instructions, so
that consecutive multiply instructions can be issued on consecutive clock cycles. Di-
vide instructions are not pipelined; an integer divide instruction preceded or followed
by an integer divide or multiply instruction results in a stall in the processor pipeline.
Note that since IMUL–IDIV and ALU–BFU are implemented as separate execution
units, an integer divide instruction preceded or followed by an ALU–BFU instruction
does not cause a delay in the pipeline.
The load/store unit handles all data transfer between the general-purpose register file
and the internal load/store bus (L-bus). The load/store unit is implemented as an inde-
pendent execution unit so that stalls in the memory pipeline do not cause the master
instruction pipeline to stall (unless there is a data dependency). The unit is fully pipe-
lined so that memory instructions of any size may be issued on back-to-back cycles.
There is a 32-bit wide data path between the load/store unit and the general-purpose
register file. Single-word accesses can be achieved with an internal on-chip data RAM,
resulting in two clocks latency. Double-word accesses require two clocks, resulting in
three clocks latency. Since the L-bus is 32 bits wide, double-word transfers require two
bus accesses. The load/store unit performs zero-fill for byte and half-word transfers
and sign extension for half-word transfers.
Addresses are formed by adding the source one register operand specified by the in-
struction (or zero) to either a source two register operand or to a 16-bit, immediate val-
ue embedded in the instruction.
The FPU contains a double-precision multiply array, the floating-point status and con-
trol register (FPSCR), and the FPRs. The multiply-add array allows the MPC555 /
MPC556 to efficiently implement floating-point operations such as multiply, multiply-
add, and divide.
The MPC555 / MPC556 depends on a software envelope to fully implement the IEEE
floating-point specification. Overflows, underflows, NaNs, and denormalized numbers
cause floating-point assist exceptions that invoke a software routine to deliver (with
hardware assistance) the correct IEEE result.
To accelerate time-critical operations and make them more deterministic, the MPC555
/ MPC556 provides a mode of operation that avoids invoking the software envelope
and attempts to deliver results in hardware that are adequate for most applications, if
not in strict conformance with IEEE standards. In this mode, denormalized numbers,
NaNs, and IEEE invalid operations are treated as legitimate, returning default results
rather than causing floating-point assist exceptions.
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
3-6