MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 129

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.5 Levels of the PowerPC Architecture
3.6 RCPU Programming Model
MPC555
USER’S MANUAL
The PowerPC architecture consists of three layers. Adherence to the PowerPC archi-
tecture can be measured in terms of which of the following levels of the architecture
are implemented:
The PowerPC architecture defines register-to-register operations for most computa-
tional instructions. Source operands for these instructions are accessed from the reg-
isters or are provided as immediate values embedded in the instruction opcode. The
three-register instruction format allows specification of a target register distinct from
the two source operands. Load and store instructions transfer data between memory
and on-chip registers.
PowerPC processors have two levels of privilege: supervisor mode of operation (typi-
cally used by the operating environment) and user mode of operation (used by the ap-
plication software). The programming models incorporate 32 GPRs, special-purpose
registers (SPRs), and several miscellaneous registers.
Supervisor-level access is provided through the processor’s exception mechanism.
That is, when an exception is taken (either due to an error or problem that needs to be
serviced, or deliberately through the use of a trap instruction), the processor begins
operating in supervisor mode. The level of access is indicated by the privilege-level
(PR) bit in the machine state register (MSR).
Figure 3-3
also illustrates the three levels of the PowerPC architecture. The numbers to the left
of the SPRs indicate the decimal number that is used in the syntax of the instruction
operands to access the register.
Note that registers such as the general-purpose registers (GPRs) are accessed
through operands that are part of the instructions. Access to registers can be explicit
(that is, through the use of specific instructions for that purpose such as move to spe-
cial-purpose register (mtspr) and move from special-purpose register (mfspr) instruc-
tions) or implicitly as the part of the execution of an instruction. Some registers are
accessed both explicitly and implicitly.
• PowerPC user instruction set architecture (UISA) — Defines the base user-level
• PowerPC virtual environment architecture (VEA) — Describes the memory model
• PowerPC operating environment architecture (OEA) — Defines the memory man-
/
instruction set, user-level registers, data types, floating-point exception model,
memory models for a uniprocessor environment, and programming model for a
uniprocessor environment.
for a multiprocessor environment, and describes other aspects of virtual environ-
ments. Implementations that conform to the VEA also adhere to the UISA, but
may not necessarily adhere to the OEA.
agement model, supervisor-level registers, synchronization requirements, and
the exception model. Implementations that conform to the OEA also adhere to the
UISA and the VEA.
MPC556
shows the user-level and supervisor-level RCPU programming models and
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
3-7