MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 147

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

SRR1 — Machine Status Save/Restore Register 1
SPRG0–SPRG3 — General Special-Purpose Registers 0–3
PVR — Processor Version Register
MSB
MSB
MSB
3.9.8 General SPRs (SPRG0–SPRG3)
3.9.9 Processor Version Register (PVR)
MPC555
USER’S MANUAL
SPRG0
SPRG1
SPRG2
SPRG3
0
0
0
Register
In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific
information, and MSR[16:31] are placed into SRR1[16:31].
SPRG0–SPRG3 are 32-bit registers provided for general operating system use, such
as performing a fast-state save and for supporting multiprocessor implementations.
SPRG0–SPRG3 are shown below.
Uses for SPRG0–SPRG3 are shown in
The PVR is a 32-bit, read-only register that identifies the version and revision level of
the PowerPC processor. The contents of the PVR can be copied to a GPR by the mf-
spr instruction. Read access to the PVR is available in supervisor mode only; write ac-
cess is not provided.
1
1
1
2
2
2
/
3
3
3
MPC556
Software may load a unique physical address in this register to identify an area of memory reserved for
use by the exception handler. This area must be unique for each processor in the system.
This register may be used as a scratch register by the exception handler to save the content of a GPR.
That GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory.
This register may be used by the operating system as needed.
This register may be used by the operating system as needed.
4
4
4
5
5
5
6
6
6
VERSION
7
7
7
8
8
8
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 3-15 Uses of SPRG0–SPRG3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
RESET: UNCHANGED
RESET: UNCHANGED
RESET: UNDEFINED
SPRG0
SPRG1
SPRG2
SPRG3
SRR1
Table
Description
3-15.
REVISION
SPR 272 – SPR 275
SPR 287
MOTOROLA
SPR 27
3-25
LSB
LSB
LSB
31
31
31