MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 157

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.11.4 Precise Exceptions
3.11.5 Exception Vector Table
MPC555
USER’S MANUAL
debug port non-maskable interrupt or machine check exception occurs during the ser-
vicing of a previous exception, the machine state information in SRR0 and SRR1 (and,
in some cases, the DAR and DSISR) may not be recoverable; the processor may be
in the process of saving or restoring these registers.
To determine whether the machine state is recoverable, the user can read the RI (re-
coverable exception) bit in SRR1. During exception processing, the RI bit in the MSR
is copied to SRR1 and then cleared. The operating system should set the RI bit in the
MSR at the end of each exception handler’s prologue (after saving the program state)
and clear the bit at the start of each exception handler’s epilogue (before restoring the
program state). Then, if an unordered exception occurs during the servicing of an ex-
ception handler, the RI bit in SRR1 will contain the correct value.
In the MPC555 / MPC556, all synchronous (instruction-caused) exceptions are pre-
cise. When a precise exception occurs, the processor backs the machine up to the in-
struction causing the exception. This ensures that the machine is in its correct
architecturally-defined state. The following conditions exist at the point a precise ex-
ception occurs:
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are
vectored. If the bit is cleared, the exception vector table begins at the physical address
0x0000 0000; if IP is set, the exception vector table begins at the physical address
0xFFF0 0000.
the exception handler routine for each exception type.
1. Architecturally, no instruction following the faulting instruction in the code
2. All instructions preceding the faulting instruction appear to have completed with
3. SRR0 addresses either the instruction causing the exception or the immediate-
4. Depending on the type of exception, the instruction causing the exception may
/
MPC556
stream has begun execution.
respect to the executing processor.
ly following instruction. Which instruction is addressed can be determined from
the exception type and the status bits.
not have begun execution, may have partially completed, or may have complet-
ed execution.
In the MPC555 / MPC556, the exception table can additionally be re-
located by the BBC module to internal memory and reduce the total
size required by the exception table (see
cation).
Table 3-21
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the exception vector offset of the first instruction of
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
4.5 Exception Table Relo-
MOTOROLA
3-35