MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 161

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.13.4 Exceptions
3.13.5 The Branch Processor
3.13.6 Instruction Fetching
3.13.7 Branch Instructions
3.13.7.1 Invalid Branch Instruction Forms
3.13.7.2 Branch Prediction
3.13.8 The Fixed-Point Processor
3.13.8.1 Fixed-Point Instructions
MPC555
USER’S MANUAL
tation-dependent software emulation interrupt. Invalid and preferred instruction forms
treatment by the MPC555 / MPC556 is described under the specific processor compli-
ance sections.
Invocation of the system software for any instruction-caused exception in the MPC555
/ MPC556 is precise, regardless of the type and setting.
The core fetches a number of instructions into its internal buffer (the instruction pre-
fetch queue) prior to execution. If a program modifies the instructions it intends to ex-
ecute, it should call a system library program to ensure that the modifications have
been made visible to the instruction fetching mechanism prior to execution of the mod-
ified instructions.
The core implements all the instructions defined for the branch processor by the UISA
in the hardware. For performance of various instructions, refer to
manual.
Bits marked with z in the BO encoding definition are discarded by the MPC555 /
MPC556 decoding. Thus, these types of invalid form instructions yield result of the de-
fined instructions with the z bit zero. If the decrement and test CTR option is specified
for the bcctr or bcctrl instructions, the target address of the branch is the new value
of the CTR. Condition is evaluated correctly, including the value of the counter after
decrement.
The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-
ready branch conditions. No prediction is done for branches to link or count register if
the target address is not ready. Refer to RCPU Reference Manual (Conditional Branch
Control) for more information.
The core implements the following instructions:
• Fixed-point arithmetic instructions
• Fixed-point compare instructions
• Fixed-point trap instructions
• Fixed-point logical instructions
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
Table 3-22
MOTOROLA
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