MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 162

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.13.9 Floating-Point Processor
3.13.9.1 General
3.13.9.2 Optional instructions
3.13.10 Load/Store Processor
MPC555
USER’S MANUAL
All instructions are defined for the fixed-point processor in the UISA in the hardware.
For performance of the various instructions, refer to
The MPC555 / MPC556 implements all floating-point features as defined in the UISA,
including the non-IEEE working mode. Some features require software assistance.
For more information refer to RCPU Reference Manual (Floating-point Load Instruc-
tions) for more information.
The only optional instruction implemented by MPC555 / MPC556 hardware is store
floating point as integer word indexed (stfiwx). An attempt to execute any other op-
tional instruction causes the implementation dependent software emulation interrupt
to be taken.
The load/store processor supports all of the 32-bit implementation fixed-point Power-
PC load/store instructions in the hardware.
• Fixed-point rotate and shift instructions
• Move to/from system register instructions
/
— Move To/From System Register Instructions. Move to/from invalid special
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of
MPC556
registers in which spr0 = 1 yields invocation of the privilege instruction error in-
terrupt handler if the processor is in problem state. For a list of all implemented
special registers, refer to
Development Support
the divisions in the divw[o][.] instruction:
0x80000000
<anything>
Then, the contents of RT are 0x80000000 and if Rc =1, the contents of bits in
CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value. If an
attempt is made to perform any of the divisions in the divw[o][.] instruction,
<anything>
contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the
correct value. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable
for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction
form is invalid. The core ignores this bit and therefore, the behavior when L =
1 is identical to the valid form instruction with L = 0
÷
÷
Freescale Semiconductor, Inc.
÷
0
0. Then, the contents of RT are 0x80000000 and if Rc = 1, the
For More Information On This Product,
-1
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
SPRs.
Table 3-2 Supervisor-Level
Table
3-22.
SPRs, and
MOTOROLA
Table 3-3
3-40