MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 167

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.15.4.2 Machine Check Interrupt
3.15.4.3 Data Storage Interrupt
MPC555
USER’S MANUAL
A machine check interrupt indication is received from the U-bus as a possible re-
sponse either to the address or data phase. It is usually caused by one of the following
conditions:
As defined in the OEA, machine check interrupts are enabled when MSR
MSR
the checkstop state. The behavior of the MPC555 / MPC556 in checkstop state is de-
pendent on the working mode as defined in
Mode
mode instead of the checkstop state. When in debug mode disable, instruction pro-
cessing is suspended and cannot be restarted without resetting the core.
An indication is sent to the SIU which may generate an automatic reset in this condi-
tion. Refer to
enabled, MSR
following registers are set.
For load/store bus cases, these registers are also set:
Execution resumes at offset 0x00200 from the base address indicated by MSR
A data storage interrupt is never generated by the hardware. The software may branch
to this location as a result of implementation-specific data storage protection error in-
terrupt.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
• The accessed address does not exist
• A data error is detected
/
ME
MPC556
Disable. When the processor is in debug mode enable, it enters the debug
= 0 and a machine check interrupt indication is received, the processor enters
Register Name
SECTION 7 RESET
ME
= 1, it is taken. If SRR1 Bit 30 = 1, the interrupt is recoverable and the
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
10:15
Other
Other
Bits
ME
Go to: www.freescale.com
2:4
LE
IP
1
Rev. 15 October 2000
Bit is copied from ILE
Set to 0
for more details. If the machine check interrupt is
Set to the effective address of the instruction that caused the
interrupt
Set to 1 for instruction fetch-related errors and 0 for load/
store-related errors
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
No change
No change
21.4.1.1 Debug Mode Enable vs. Debug
RI
Description
MOTOROLA
ME
= 1. If
IP
.
3-45